1. Field of the Invention
The present invention generally relates to an electrostatic discharge (ESD) protection circuit. More specifically, the present invention relates to an ESD protection circuit with a tunable trigger voltage.
2. Description of the Related Art
ESD protection is an important consideration in the sub-micron technology. FIG. 1 is a cross-section diagram of a lateral semiconductor-controlled-rectifier (LSCR) according to the prior art. Numeral 1 represents a core circuit powered by power sources VSS and VDD. Numeral 2 represents a pad. A lateral semiconductor-controlled-rectifier (LSCR) is connected to the pad 2. During an ESD event, ESD stress is released through the turn-on of the LSCR. Thus, the core circuit 1 is prevented from damage by ESD event.
Please refer to FIG. 1. An n-type well region 11 is formed in the p-type substrate 10. A p+ doped region 12 is formed inside the n-type well region as an anode of the LSCR 3. A n+ doped region 13 is formed inside the p-type substrate 10 as a cathode of the LSCR 3. The p+ doped region 13 is coupled to the n-type well region via an n+ contact region 14. The n+ doped region 13 is coupled to the p-type substrate 10 via a p+ contact region.
The LSCR 3 in FIG. 1 comprises two parasitic bipolar transistors, T1 and T2. As shown in the diagram, the p+ doped region 12, the n-type well region 11 and the p-type substrate 10 form the emitter, the base and the collector of a PnP bipolar transistor Tl, respectively. The n-type well region 11, the p-type substrate 10 and the n+ doped region form the emitter, the base and the collector of a npn bipolar transistor T2. The resistors Rwell and Rsub represent the spreading resistance of the n-type well 11 and the p-type substrate 10, respectively. As shown in FIG. 1, n+ contact region 14 and the p+ contact region 12 both connect to the pad 2. The n+ doped region 13 and the p+ contact region 15 both connect to the power source VSS. The power source VSS is usually grounded in normal operation without ESD event.
FIG. 2 is a diagram of I-V curves for an LSCR. During an ESD event, the power sources VDD and VSS are all disconnected and floating. When a positive pulse relative to the power source VSS happens at the pad 2, the LSCR 3, which has a trigger voltage Vtrig and a trigger current Itrig, turns on to release the ESD stress because of the avalanche breakdown between the n-type well region 11 and the p-type substrate 10. Then, the LSCR 3 clamps the voltage drop between the anode 12 and the cathode 13 in a holding voltage Vh to prevent the core circuit 1 from damage caused by ESD stress. When a negative pulse relative to the power source VSS happens at the pad 2, the junction between the n-type well region 11 and the p-type substrate 10 is forward biased to release the ESD stress and protect the core circuit 1. The I-V curve of the LSCR 3 is shown in FIG. 2. The trigger voltages Vtrig, the breakdown voltage between the n-type well 11 and the p-type substrate 10, is around 30 to 50 volt for 0.5 um technology.
FIG. 3 is a cross-section diagram of a field-oxide-edge-triggered SCR according to the prior art. FIG. 4 is a cross-section diagram of a gate-aided SCR according to the prior art. However, the trigger voltage of around 30 to 50 volt is too high and the core circuit would be damaged before the LSCR 3 is triggered. Thus, FIG. 3 shows an improvement of FIG. 1. As shown in FIG. 3, a field-oxide 20 and an n+ breakdown region 22 adjacent to the field-oxide 20 are added. Since the p-type substrate 10 under the field-oxide 20 has a higher doped concentration to form channel stoppers, the breakdown voltage of the junction between the n+ breakdown region 22 and the substrate at the edge of the field oxide will breakdown earlier to trigger the LSCR. FIG. 4 shows another improvement of the LSCR in FIG. 1. The breakdown voltage the source/drains and the substrate of a MOS transistor is lower than that between the n-type well 11 and the p-type substrate 10. The trigger voltages Vtrig of the LSCRs in FIG. 3 and FIG. 4 are around 15 to 20 volt.
However, based upon a fixed structure dimension and a given process technology, each of the ESD protection circuits mentioned has only a single ESD protection performance. For example, the SCRs suitable for 5-volt input/outputs (I/Os) may not suit 12-volt I/Os. Engineers must re-design the layout, test the ESD performance and spend much time and money to obtain two kinds of ESD protection circuits to meet different requirements.
Therefore, an object of the present invention is to provide an ESD protection. circuit with a non-volatile memory inside. By adjusting the charge in the floating gate of the non-volatile memory, different trigger voltages for different requirements can be achieved.
The present invention achieves the above-indicated objects by providing an electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a semiconductor-controlled-rectifier (SCR) and a non-volatile memory. The SCR comprises an anode, an anode gate and a cathode. The anode and the cathode are coupled to a first node and a second node, respectively. The non-volatile memory comprises a floating gate and two source/drains. The two source/drains are respectively coupled to the cathode and the anode gate. The floating gate comprises a predetermined charge to decrease the trigger voltage of the SCR.
In view of structures, the present invention provides an electrostatic discharge protection circuit comprising an n-type semiconductor layer, a p-type semiconductor layer, a p-type doped region and a non-volatile memory. The n-type semiconductor layer comprises a first contact region coupled to a first node. The p-type semiconductor layer adjacent to the n-type semiconductor forms a junction therebetween and comprises a second contact region. The p-type doped region is positioned in the n-type semiconductor region and is coupled to the first node. The non-volatile memory is positioned in the p-type semiconductor layer and comprises a floating gate and two source/drains. One source/drain is coupled to the n-type semiconductor layer. Another source/drain and the second contact region are coupled to a second node. The floating gate comprises a predetermined charge to increase the leakage current in one of the two drain/sources during an ESD event.
If the voltage at the first node exceeds a predetermined voltage defined by the predetermined charge in the floating gate, gate-induced-drain-leakage occurs to lower the voltage of the n-type semiconductor layer near the junction. Furthermore, GIDL will flow through the p-type semiconductor layer to raise the voltage of the p-type semiconductor layer near the junction. Both the results can trigger the SCR to protect the core circuit.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.